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Intel Sapphire Rapids Enterprise CPUs Confirmed With On-Package HBM Memory Support
The end of the year is typically thin on interesting news in the technology sector, as companies opt to wait for the Consumer Electronics Show (CES) in January to make any major announcements or product unveils. There are exceptions, however. Just before we ring in another year, Intel has posted an interesting document that essentially confirms its upcoming Xeon Scalable processors based on Sapphire Rapids will support on-package high bandwidth memory (HBM).
While previously rumored, this is a feature Intel has not explicit stated up to this point. During its Architecture Day 2020 event this past summer, Intel talked a little about Sapphire Rapids (among other things), noting it is based on an 10-nanometer enhanced SuperFin technology, which should yield better performance and power characteristics.
Compute Express Link Controller IP Designed to the CXL Link Specification with AMBA Interfaces Optimized for SoC Implementations XpressLINK-SOC™ is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. The XpressLINK-SOC Controller IP leverages PLDA s silicon proven XpressRICH-AXI Controller for PCIe 5.0 architecture for the CXL.io path, and adds the CXL.cache and CXL.mem paths specific to CXL. XpressLINK-SOC supports the AMBA® AXI™ Protocol Specification for CXL.io traffic, and either Intel CXL-cache/mem Protocol Interface (CPI) or a AMBA® AXI™ Protocol Specification for CXL.mem and CPI interface for CXL.cache traffic, or the AMBA® CXS Protocol Specification. XpressLINK-SOC also complies with the Intel PHY Interface for PCI Express (PIPE) specification version 5.x and supports the PIPE LPC and SERDES modes. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirement