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New Electronics - Andes Technology and GHS to deliver advanced automotive safety platform for RISC-V - Vimarsana News

New Electronics - Andes Technology and GHS to deliver advanced automotive safety platform for RISC-V

Andes Technology, a RISC-V CPU IP vendor and a founding member of RISC-V International, and Green Hills Software, are offering an integrated platform for safe and secure computing on the AndesCore 25-Series family of RISC-V cores.

RISC-V Summit China 2022 Announces Agenda - High-Performance Computing News Analysis - Vimarsana News

RISC-V Summit China 2022 Announces Agenda - High-Performance Computing News Analysis

Shanghai, August 12, 2022 – The RISC-V Summit China 2022 (Aug. 24-26) today announced its 2022 agenda, including keynotes, tutorials, and technical [...]

Andes Technology and IAR Systems Develop the First RISC-V Automotive CPU, To Accelerate Time To Market - Vimarsana News

Andes Technology and IAR Systems Develop the First RISC-V Automotive CPU, To Accelerate Time To Market

Andes Technology and IAR Systems announce the development of the AndesCore RISC-V automotive CPU IP functional safety certified

RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 - Vimarsana News

RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021

Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical Applications Nuremberg, Germany – June 21, 2022 – RISC-V International, the global open-design standards pioneer, announced its first four specification and extension approvals of 2022 – Efficient…

Embedded World: RISC-V rattifies Efficient Trace and Supervisor Binary Interface - Vimarsana News

Embedded World: RISC-V rattifies Efficient Trace and Supervisor Binary Interface

At Embedded World this morning, RISC-V International announced approval of its E-Trace (Efficient Trace for Risc-V) and SBI (RISC-V supervisor binary inter