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Codasip, the leading supplier of customizable RISC-V processor IP, today announced that Dr Karel Masařík, company founder responsible for the development of Codasip’s core technology, has been elected to the RISC-V Technical Steering Committee (TSC) by RISC-V International Strategic members.
Munich Germany, October 28, 2021 – Codasip, the leading supplier of customizable RISC-V processor IP, today announced that Dr Karel Masařík, company founder responsible for the development of Codasip’s core technology, has been elected to the RISC-V Technical Steering Committee (TSC) by RISC-V International Strategic members...
The L10 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage ...
The H50X is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space. The core has ...
64-bit RISC-V application processor core with 7-stage pipeline The A70X is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace. Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits. View see the enti...