GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in TSMC 28HPC+
For Gigabit 10/100/1000 Ethernet applications, the GPHY is a highly integrated single chip. It is a singleport, IEEE 802.3u/ab compatible, power efficient ...
Source: design-reuse.com
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HW/SW interface foundation for design innovation
It is typical for the HW/SW interface (HSI) of a system-on-chip to grow exponentially in complexity with each new generation. The HSI database has become ...
Source: design-reuse.com
PUSCH Decoder for 3GPP 5G NR
<b>3GPP compliant coding and modulation for Physical Shared Channels</b> The Physical Uplink Shared Channel (PUSCH) is used to for uplink data which ...
Source: design-reuse.com
RISC-V System IP IP Core
Streamline Ventana technology integration into high-performance systems, fully leveraging third-party IP, while applying RISC-V simplifying system principles. ...
Source: design-reuse.com
12-bit 16-Gsps DAC IP Core
Unleash the power of precision and innovation with the NS_TX_16G_T16, a state-of-the-art 12-bit, 16-Gsps Digital-to-Analog Converter (DAC) array. ...
Source: design-reuse.com