MIPI D-PHY CSI-2 RX (Receiver) in TSMC 16FFC
He MXL-DPHY-CSI-2-RX-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for ...
Source: design-reuse.com
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External Compensated LDO - 300mA Output
The ODT-LDO-EC-300M-16FFCT is a low dropout (LDO), linear regulator for integration in a SoC. The LDO uses advanced control techniques to achieve excellent ...
Source: design-reuse.com
LEOphy - 5G NTN complete high PHY solution
As the wireless telecommunication industry evolves to become open, virtualized and disaggregated, there is an increased need for interoperable solutions ...
Source: design-reuse.com
eCPRI IP Core
Comcores eCPRI core is a highly scalable and silicon-agnostic implementation of the eCPRI standard targeting any ASIC, FPGA or ASSP technologies. The ...
Source: design-reuse.com
HDMI 2.1 IP Core IP Core
The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices. Supporting uncompressed video formats to 8K60 4:2:0 and beyond for ...
Source: design-reuse.com