28G LR Multi-Protocol SerDes (MPS) PHY
The 28 Gbps Multi-Protocol SerDes (MPS) PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling ...
Source: design-reuse.com
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eUSB2 PHY IP Core
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was ...
Source: design-reuse.com
AI Inference IP. Ultra-low power, tiny, std CMOS. ~ 100K parameter RNN
Blumind's all analog AMPL™ neural signal processor IP for edge AI applications is designed on standard advanced node CMOS technology and can be integrated ...
Source: design-reuse.com
AHB MultiMatrix Fabric IP Core
The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters. The off-the-self configuration ...
Source: design-reuse.com
16Kx33 Bits OTP (One-Time Programmable) IP, TSMC 40LP 1.1V/2.5V
The ATO016KX33TS040LLP7ZA is organized as 16K-bits by 33 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSMC 40nm ...
Source: design-reuse.com