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Synopsys, Inc. (NASDAQ:SNPS) Q4 2023 Earnings Call Transcript

Operator: Ladies and gentlemen, welcome to the Synopsys Earnings Conference Call for the Fourth Quarter and Fiscal Year 2023. At this time, all participants are in a listen-only mode. ....

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Synopsys' (SNPS) Design Flows Get Certification for N2 Process

Synopsys' (SNPS) digital and analog design flows receive the certification for TSMC's N2 process technology. ....

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Efficient Top-Level Interconnect Planning and Implementation with Synopsys IC Compiler II

Jiangtao Meng, Sr. R&D Manager at Synopsys, discusses how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning (TIP) technology to accelerate project schedules while achieving highest performance designs. ....

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Synthesis Methodology & Netlist Qualification

The main objective of this article is to explain synthesis flow and post-synthesis netlist quality checks. In ASIC flow, synthesis is the part of the front-end design, while the back-end design takes the synthesized netlist as an input. So, the synthesized netlist should meet all netlist quality checks to reduce multiple iterations, which reduces the turnaround time and efforts. ....

Vallabh Vidyanagar , Ashish Trapasiya , Dhanyakumar Shah , Synopsys Design , Fusion Compiler , For Physical , Aware Synthesis , Wire Load Model , Physical Aware , Connect Supply Net , Logic Equivalence Checks , Senior Physical Design Engineer ,

Samsung Foundry Adopts Leading Voltage-Timing Signoff Solution from Synopsys, Ansys

Samsung Foundry Adopts Leading Voltage-Timing Signoff Solution from Synopsys, Ansys
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