Compute Express Link (CXL) 3.1 Controller IP Core
The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® ...
Source: design-reuse.com
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Synchronous Ethernet (SyncE) ESMC and Enhanced ESMC core
NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ...
Source: design-reuse.com
FlexRay Controller IP Core
Logic Fruit Technologies has designed FlexRay RTL IP Core, supporting data rate up to 10 Mbps. FlexRay, a high-speed protocol for advanced vehicles, ...
Source: design-reuse.com
Low Dropout (LDO) Capless Regulator IP Core
The ODT-LDO-IC-250M-12 is a low dropout (LDO), linear regulator for integration in a SoC. The LDO uses advanced control techniques to achieve excellent ...
Source: design-reuse.com
High Bandwidth Memory (HBM) 3 PHY
The High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. The memory subsystem ...
Source: design-reuse.com