Avery Design Debuts CXL™ 2.0 System-level VIP Simulation Solution
Tewksbury, MA., April 15, 2021 — Avery Design Systems, a leader in functional verification solutions, today announced its CXL
TM 2.0 system-level simulation solution. The comprehensive offering supports the co-simulation of a CXL-aware Linux kernel and QEMU x86 virtual host system emulator with its SystemVerilog CXL Host VIP. The solution enables pre-silicon hardware-software validation of CXL 2.0 Type 3 memory expansion system designs, accelerating development time and providing an efficient approach to customization and application development for systems using the CXL 2.0 interface standard
“QEMU-CXL co-simulation creates the most complete and accurate representation of the CXL-enabled reference system environment from which to verify CXL 2.0 Type 3 SoC hardware RTL and software,” said Chris Browy, Vice President Sales and Marketing at Avery Design Systems. “Early integration of the actual hardware and software enables pre-silicon co-verification and rigorous compliance testing that accelerates the development schedule and dramatically reduces bug fix times and iterations.”