Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution

Formal verification techniques have been developed using mathematical proof rather than simulation or test vectors to provide a higher level of verification confidence on properties. For example, the implementation can be either a Verilog RTL module or an abstract version of a particular design, while the specification is typically a set of properties that needs to be verified and expressed suitably. So, formal verification provides a complete verification of each specification property under considering corner cases even without test vectors.

Related Keywords

India ,Priyambada Mishra ,Consumer Electronics ,Bachelor Of Technology ,Charotar University Of Science ,Equivalence Check ,Finite State Diagram ,Binary Decision Diagram ,Finite State Machine ,Register Transfer Level ,Fusion Compiler ,Synopsys Formality ,Charotar University ,Understanding ,Logic ,Equivalence ,Check ,Ec ,Low ,End ,Its ,Challenges ,Roposed ,Solution ,