Architectural Validation News Today

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest RISC-V test suites and updates to the free riscvOVPsimPlus reference model, simulator and test suites. Independently developed Verification IP (VIP) plays an important role in any verification plan since RISC-V developers’ interpretation of the specification are best tested against an independent reference. Architectural Validation…

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the beta release of the ImperasDV architectural validation test suites for RISC-V Physical Memory Protection (PMP). The open standard ISA (Instruction Set Architecture) of RISC-V offers developers a wide range of standard extensions and options that support the design of an optimized processor while…

Oxford, United Kingdom, November 29th, 2021 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the processor technology company focused on the commercialization of RISC-based processor architectures and IP cores, the continuation and extension to the long-standing relationship with simulation and verification support for RISC-V. Since 2010, MIPS has partnered with Imperas…