HBM2/2E Memory PHY IP Core
Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor and power-efficient ...
Source: design-reuse.com
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MIPI D-PHY Receiver IP Core
The MXL-DPHY-CSI2-RX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for ...
Source: design-reuse.com
MIPI M-PHY - TSMC 40nm IP Core
MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration ...
Source: design-reuse.com
HBM3 PHY
The Rambus High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. The memory ...
Source: design-reuse.com
MIPI D-PHY Transmitter in TSMC 28nm LP
The MXL-PHY-MIPI-UNIVERSAL-T-028LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Standard ...
Source: design-reuse.com
UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
The Universal Flash Storage 2.0 (UFS 2.0) is a simple but high performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.
Universal Flash Storage Controller Interface Unified Memory Architecture Fs 2 1 Host Rfs 2 1 Memory Storage
Source: design-reuse.com
HBM3 PHY
The Rambus High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. The memory ...
Source: design-reuse.com
MIPI D-PHY Receiver IP Core
The MXL-DPHY-CSI2-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. The ...
Source: design-reuse.com
UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8
Arasans Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host processing ...
Universal Flash Storage Controller Interface Unified Memory Architecture Fs 3 0 Host Fs 2 1 Host Rfs 2 1
Source: design-reuse.com
MIPI D-PHY DSI Receiver for Automotive
The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1. ...
Source: design-reuse.com