Reportable, Inc.: Avery Design Debuts CXL 2.0 System-level VIP Simulation Solution
Tewksbury, Massachusetts (Newsfile Corp. - April 15, 2021) - Avery Design Systems, a leader in functional verification solutions, today announced its CXLTM 2.0 system-level simulation solution. The comprehensive offering supports the co-simulation of a CXL-aware Linux kernel and QEMU x86 virtual host system emulator with its SystemVerilog CXL Host VIP. The solution enables pre-silicon hardware-software validation of CXL 2.0 Type 3 memory expansion system designs, accelerating development time and providing an efficient approach to customization and application development for systems using the CXL 2.0 interface standard. To view the full announcement, including downloadable images, bios, and more, click here.
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Avery Design Announces CXL™ 2.0 VIP
January 22, 2021 GMT
TEWKSBURY, Mass. (BUSINESS WIRE) Jan 22, 2021
Avery Design Systems, leader in functional verification solutions today announced availability of CXL 2.0 VIP. Computer Express Link™ (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices
Avery provides a complete System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for PCIe® 5.0 and CXL 2.0/1.1 for CXL host, Type 1-3 devices, switches, and retimers. The CXL 2.0 VIP adds key CXL 2.0 features including