CodaCache™ Last Level Cache IP IP Core
CodaCache is a configurable, standalone, non-coherent cache IP that delivers unique business value through its advanced last-level cache (LLC) architecture, ...
Source: design-reuse.com
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H8SX CPU subsystem (H8SX C3000) IP
H8SX is a high speed 32-bit CPU, which is upward-compatible with H8/300, H8/300H and H8S CPUs on an object level. This subsystem IP supports many and ...
Source: design-reuse.com
CRYSTALS-Dilithium - Post-Quantum Digital Signature IP Core
Post-quantum CRYSTALS-Dilithium Digital Signature IP Core from ResQuant supports key generation, signing and signature verification operations for II, ...
Us National Security Agency Dilithium Digital Signature Digital Signatures Security Agency Post Quantum Public Key
Source: design-reuse.com
Enhanced Neural Processing Unit for safety providing 16,384 MACs/cycle of performance for AI applications
The ASIL B or D Ready DesignWare ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of Advanced Driver ...
Metaware Mx Development Toolkit For Safety Advanced Driver Assistance Systems Neural Processing Unit Ai Processor Nhanced Neural Processing Unit For Safety Providing 16 384 Macs Cycle Of Performance For Ai Applications
Source: design-reuse.com
USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use ...
Macrocell Interface Plus Full Speed Low Speed Non Return To Zero Inverted Electro Static Discharge Usb Phy
Source: design-reuse.com
56Gbps LR SerDes IP on TSMC 16/12nm
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 112G data rates. Features include the lowest power ...
Serdes Technology Company Multi Rate Serdes Dc 2 5g Dc 5g Adc 10g 6gbps Lr Serdes Ip On Tsmc 16 12nm Ip 56mrt16c K11
Source: design-reuse.com
3D GPU supporting OpenGL ES2.0 capability
The DMP ant300 is the world’s smallest class 3D graphics IP core supporting OpenGL ES2.0 capability. It is the premiere solution for popular ASIC/ASSP/SoC/FPGA ...
Source: design-reuse.com
PVT Controller (Series 5) (Sub-system for complete PVT monitoring), TSMC N3E
The PVT Controller provides a standard digital interface to the embedded Process, Voltage and Temperature (PVT) sensing Sub-System used to increase System ...
Synopsys Designware In Chip Sensing Synopsys Silicon Lifecycle Management Pvt Controller Pvt Sensor Pvt Sensors
Source: design-reuse.com
Tessent in-life monitoring IP Core
The Tessent Embedded Analytics solution can be used to produce health and operational metrics throughout the lifecycle of an SoC. Embedded software based ...
Source: design-reuse.com
NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
NeuPro-M™ redefines high-performance AI (Artificial Intelligence) processing for smart edge devices and edge compute with heterogeneous coprocessing, ...
Source: design-reuse.com