AXI2AXI bridge IP Core
Vtool AXI2AXI bridge provides up-size and down-size translation of AXI transaction between AXI master and AXI slave of different data width while taking ...
Source: design-reuse.com
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MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
The MXL-CPHY-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave supporting camera ...
Source: design-reuse.com
4K x 8 Bits OTP IP, GF22nm FDX 0.8V/1.8
The AT4K8G22FDX0AA is organized as 4K-bits by 8 one-time programmable in mode. This is a kind of non-volatile memory fabricated in 22nm standard CMOS ...
Source: design-reuse.com
Ethernet Switch / Router IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide ...
Packet Architects Advanced Qos Flow Control Thernet Switch Router Ip Core Efficient And Massively Customizable 3qos 1 P Core
Source: design-reuse.com
800G Ethernet IP for AI Application
The Alphawave IP OmegaCORE 800G_AX is a cutting-edge solution with the latency, power, and area highly optimized for artificial intelligence applications. ...
Alphawave Ip Omega Physical Coding Sublayer Forward Error Correction Media Access Control 00g Ethernet Ip For Ai Application Megacore 800g Ax
Source: design-reuse.com
PCIe 5.0 PHY on TSMC N6
The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...
Source: design-reuse.com
CAN FD Light Bus Controller IP Core
Arasan’s Controller Area Network – Flexible Data-Light (CAN-FD Light) Controller IP implements the CAN FD-Light (CIA 604-1) protocol. It can be integrated ...
Area Network Controller Area Network Flexible Data Light Flight Controller Control Area Network An Fd Light Bus Controller
Source: design-reuse.com
Deep learning accelerator for edge and end-point inference
AndesAIRE™ AnDLA™ I350 is a deep learning accelerator (DLA) designed to enable high performance-efficient and cost-sensitive AI solutions for edge ...
Tensorflow Lite Direct Memory Access Deep Learning Accelerator Risc V Igh Performance Efficient Deep Learning Accelerator For Edge And End Point Inference Ndesaire Andla I350
Source: design-reuse.com
LTE turbo decoder IP Core
TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for FPGAs. Its unique pipe-line architecture enables to reach very high clock frequencies ...
Source: design-reuse.com
PCIe Gen6 Controller IP Core
Our latest PCIe gen 6 controller IP, which is "NoC aware", provides a high-speed interface for efficient data transfer and system communication, supporting ...
Source: design-reuse.com