Page 4 - Forward Error Correction News Today

Rambus, a chip and silicon IP provider, is making available its PCI Express (PCIe) 6.0 Interface subsystem comprised of PHY and controller IP.

Rambus announces its next-gen PCIe 6.0 interface subsystem for high-performance data centers and AI SoCs of the future, with up to 64 GT/s ready.

Delivers data rate of up to 64 GT/s for high-performance workloads Supports the full feature set of PCIe 6.0 with PHY support for CXL 3.0 Offers complete IP solution optimized for latency, power, and area Provides cutting-edge security to protect valuable data assets.

ATSC 3.0 deployments are accelerating in the U.S., driving the need for solutions that optimize the delivery of new revenue-enhancing services. At NAB Show New

/PRNewswire/ -- Anritsu Company announces that its Signal Quality Analyzer-R MP1900A now supports the PCI Express® 6.0 (PCIe® 6.0) Base Specification Receiver...

The company will also feature its StreamScope XM 3.0 monitor and enterprise platform

As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability.

Avant Technology Inc., a professional EDA tool & Silicon IP distributor based in Hsinchu, Taiwan, is now a representing partner of NSITEXE, Inc., a wholly owned subsidiary of Denso Corporation that develops and sells high efficiency processor IP for embedded systems. Avant and NSITEXE will work together to serve the customers in Taiwan and China.

In 2021, PCI-SIG® released the latest version of the PCI Express® specification PCIe® 6.0. PCIe 6.0 has a raw data rate of 64 GT/s and double the bandwidth ...

The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.