PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL
The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP includes mixed-signal circuits to ...
Physical Media Attachment Physical Coding Sublayer Electrostatic Discharge Pcie2 0ip Pcie3 0ip Cie 3 1 Ip
Source: design-reuse.com