Page 21 - P Core News Today

The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture and simple programmer’s ...

The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP includes mixed-signal circuits to ...

CT23302 provides means to determine the leakage current of some pre-defined MOS devices in the TSMC 28n technology node. It is also possible to estimate ...

The Synopsys USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules ...

He MXL-DPHY-CSI-2-RX-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for ...

The ODT-LDO-EC-300M-16FFCT is a low dropout (LDO), linear regulator for integration in a SoC. The LDO uses advanced control techniques to achieve excellent ...

As the wireless telecommunication industry evolves to become open, virtualized and disaggregated, there is an increased need for interoperable solutions ...

Comcores eCPRI core is a highly scalable and silicon-agnostic implementation of the eCPRI standard targeting any ASIC, FPGA or ASSP technologies. The ...

The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices. Supporting uncompressed video formats to 8K60 4:2:0 and beyond for ...

Synopsys’ Controller IP for Bluetooth Low Energy, Thread, and Zigbee delivers secure, concurrent wireless connectivity for Internet of Things (IoT) ...