Page 34 - P Core News Today

The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use ...

The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC). The system has an internal state machine ...

028TSMC_PVT_04 is a unique solution intended to continuously monitor IC status at several on-die locations. It is able to detect manufacturing process ...

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, ...

Qualitas Semiconductor's TCON eRVDS TX PHY IP is an advanced chip-on glass (ACOG) and chip-on-film(COF) transmitter embedded into the timing controller ...

QuiddiKey is Intrinsic ID hardware IP which enables device manufacturers and designers to secure their products with internally generated, device-unique ...

The ODT-LDO-IC-60M-7T-122 is a low dropout (LDO), linear regulator for integration in a SoC. The LDO uses advanced control techniques to achieve excellent ...

CT20603 IP implements a dual-role capable eUSB2 repeater enabling an eUSB2 PHY in SOCs to support connections with USB2.0 compliant hosts and peripherals ...

1-VIA’s VSCOM4L400ALDO0V6 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulation across a wide range ...

The number of connected devices, machines or sensors that are linked with each other over open communication networks on the internet of things (IoT) ...