Page 41 - P Core News Today

The MXL-CPHY-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave supporting camera ...

The AT4K8G22FDX0AA is organized as 4K-bits by 8 one-time programmable in mode. This is a kind of non-volatile memory fabricated in 22nm standard CMOS ...

Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide ...

The Alphawave IP OmegaCORE 800G_AX is a cutting-edge solution with the latency, power, and area highly optimized for artificial intelligence applications. ...

The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...

Arasan’s Controller Area Network – Flexible Data-Light (CAN-FD Light) Controller IP implements the CAN FD-Light (CIA 604-1) protocol. It can be integrated ...

AndesAIRE™ AnDLA™ I350 is a deep learning accelerator (DLA) designed to enable high performance-efficient and cost-sensitive AI solutions for edge ...

TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for FPGAs. Its unique pipe-line architecture enables to reach very high clock frequencies ...

Our latest PCIe gen 6 controller IP, which is "NoC aware", provides a high-speed interface for efficient data transfer and system communication, supporting ...

LeapMind is currently developing "Efficiera", an AI inference accelerator IP with ultra low power consumption, optimized for CNN inference processing ...