320Gbps Ethernet Switch IP Core
Packet Architects offers a series of high speed switching IPs which are developed using the unique FlexSwitch toolchain. The toolchain allows a fast and ...
Source: design-reuse.com
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Maestro DLL (Clock Domain Crossing, dynamic compensation, clock distribution network)
If you are considering a DLL for your clock network management, take a look at Maestro! Maestro solves chip-level clock network challenges in high-performance ...
Network On Chip Intelligent Clock Network Aestro Dll Clock Domain Crossing Dynamic Compensation Lock Distribution Network Ovellus Maestro
Source: design-reuse.com
Universal IoT Security Platform IP Core
Our patented universal IoT security platform that works with any root-of-trust for easy-to-use, scalable end-to-end security. QuarkLink is our software-based ...
Source: design-reuse.com
High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
The SuperRAM implements a hardware accelerator for zram compression and decompression. SuperRAM implements a ZeroPoint proprietary compression algorithm ...
Igh Performance And Low Latency Hardware Accelerated Zram Zswap At Unmatched Power Efficiency P Core Ilicon Ip Emiconductor Ip
Source: design-reuse.com
Distributed Thermal Sensor (DTS) Non-Deep NWELL, TSMC N4P
The highly granular DTS offers a significant area reduction in comparison to some standard in-chip thermal sensor solutions and supports high accuracy ...
Synopsys Designware In Chip Sensing Synopsys Silicon Lifecycle Management Distributed Thermal Pvt Sensor Pvt Sensors
Source: design-reuse.com
RISC-V 64-bit Standard CPU IP Core
The NS 72 supports the RV64GCV instruction set and is an application CPU supporting a variety of operating systems, while maintaining Akaria’s functional ...
Source: design-reuse.com
Complete high PHY solution that minimizes BLER and power for 5G satellites
As the wireless telecommunication industry evolves to become open, virtualized and disaggregated, there is an increased need for interoperable solutions ...
Omplete High Phy Solution That Minimizes Bler And Power For 5g Satellites P Core Ilicon Ip Emiconductor Ip
Source: design-reuse.com
AI accelerator (NPU) IP - 16 to 32 TOPS
The Origin E6 is designed for applications where performance and power consumption are primary design goals, including smartphones, tablets, and edge ...
Natural Language Processing Ai Accelerator Inference Accelerator Neural Engine Deep Learning Accelerator Neural Network Accelerator
Source: design-reuse.com
USB3.2 PHY IP on Samsung 4LPE
The DesignWare® SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes ...
Implementer Forum Usb Phy Ynopsys Usb3 2 Phy Ip On Samsung 4lpe Wc Usbc32sspphy Ss4lpens P Core Ilicon Ip
Source: design-reuse.com
Single-issue, in-order, 3-stage pipeline and RISC-V compatible MCU-class core, Ultra-low power RISC-V microcontroller
RiVAI-E1 is a single-issue, in-order, 3-stage pipeline and RISC-V compatible MCU-class core. It is industry-grade and silicon-proven. It supports RV32I ...
Riscv Microcontroller Risc V Ultra Low Power Single Issue Gin Order Ltra Low Power Riscv Microcontroller
Source: design-reuse.com