Posted July 19th, 2021 for Imperas
Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing.
Oxford, UK – July 19th, 2021 – Imperas Software Ltd ., the leader in RISC-V processor verification technology, announces the latest updates to
riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites. The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite helps ensure implementations have a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specification.
Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites
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RISC-V reference models certified for the new extension
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Andes certifies Imperas RISC-V Reference Models for SIMD/DSP extension Imperas Software has announced that Andes Technology, a supplier of 32/64-bit RISC-V CPU cores and a member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension.
As a consequence, developers will now be able to use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.
The open standard RISC-V ISA (Instruction Set Architecture) has a modular structure based on multiple independent extensions that offer dedicated and enhanced functionality to optimize a processor for the target application. The SIMD/DSP extension, designated as âPâ in the specification description, supports efficient data processing applications and real-time requirements.