Cadence Integrity 3D-IC Platform Supports TSMC 3DFabric™ Technologies for Advanced Multi-Chiplet Designs
Highlights: ● The Cadence 3D-IC solution centers on the Integrity 3D-IC platform, which provides integrated planning, implementation and system analysis to optimize PPA for multi-chiplet systems ● The Tempus Timing Signoff Solution with inter-die analysis and STA technologies results in faster time to tapeout ● The Voltus IC Power Integrity Solution, tightly coupled with the…
Chin Chi Teng Suk Lee Digital Signoff Group At Cadence Design Infrastructure Management Division Cadence Design Systems Inc Tempus Timing Signoff Solution
Source: eejournal.com