Electronics Weekly is proud to reveal the Shortlist for this year’s Elektra Awards, the industry’s largest technology and business awards. The judges have
The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques. Cadence, Siemens, and Synopsis discussed differing aspects for ongoing test challenges.
For example, a scan-based failure diagnosis tool s accuracy, resolution, and performance are extremely critical for enabling faster silicon chip testing and improving overall yields. Scan-based diagnostic methods are used to identify and locate semiconductor defects on devices that fail the manufacturing test or are returned from the field. But selecting the proper test devices for failure analysis is a challenge. To address this problem, some semiconductor manufacturers have incorporated scan diagnosis into the yield analysis process.