April 30, 2021
Astera Labs and Avery Design Partner on CXLTM 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications
Astera Labs Aries Smart Retimers resolve signal integrity issues for high-performance server, storage, cloud and workload optimized systems
Avery PCIe and CXL Verification IP enabled Astera Labs to get to market faster
Tewksbury, MA., April 28, 2021 Avery Design Systems, a leader in functional verification solutions, today announced that Astera Labs, a pioneer in connectivity solutions for intelligent systems, successfully used Avery’s Compute Express Link™ (CXLTM) 2.0 and PCI Express® (PCIe®) 5.0 Verification IP (VIP) and services in developing its Aries Smart Retimer portfolio.
Reportable, Inc : Astera Labs and Avery Design Partner on CXL 2 0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications
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Avery Design debuts CXL 2 0 System-level VIP simulation solution
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Reportable, Inc.: Avery Design Debuts CXL 2.0 System-level VIP Simulation Solution
Tewksbury, Massachusetts (Newsfile Corp. - April 15, 2021) - Avery Design Systems, a leader in functional verification solutions, today announced its CXLTM 2.0 system-level simulation solution. The comprehensive offering supports the co-simulation of a CXL-aware Linux kernel and QEMU x86 virtual host system emulator with its SystemVerilog CXL Host VIP. The solution enables pre-silicon hardware-software validation of CXL 2.0 Type 3 memory expansion system designs, accelerating development time and providing an efficient approach to customization and application development for systems using the CXL 2.0 interface standard. To view the full announcement, including downloadable images, bios, and more, click here.
Avery Design Debuts CXL™ 2.0 System-level VIP Simulation Solution
Tewksbury, MA., April 15, 2021 Avery Design Systems, a leader in functional verification solutions, today announced its CXL
TM 2.0 system-level simulation solution. The comprehensive offering supports the co-simulation of a CXL-aware Linux kernel and QEMU x86 virtual host system emulator with its SystemVerilog CXL Host VIP. The solution enables pre-silicon hardware-software validation of CXL 2.0 Type 3 memory expansion system designs, accelerating development time and providing an efficient approach to customization and application development for systems using the CXL 2.0 interface standard
“QEMU-CXL co-simulation creates the most complete and accurate representation of the CXL-enabled reference system environment from which to verify CXL 2.0 Type 3 SoC hardware RTL and software,” said Chris Browy, Vice President Sales and Marketing at Avery Design Systems. “Early integration of the actual hardware