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Coronavirus outbreak in Taiwan threatens to worsen global semiconductor shortage
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Week In Review: Manufacturing, Test
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Customizing Chips For Power And Performance
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Chemical mechanical polishing (CMP) – also known as planarization – has long been the most commonly employed technique for smoothing and flattening wafer surfaces during the fabrication of semiconductor integrated chips (IC). This approach has been common practice for decades.
During this time, post-CMP evaluation has become the standard means of ensuring adequate planarity of IC layers, as well as the most common approach to confirming their compliance with planarity requirements.
Conventional post-CMP process evaluation methods have analytical limitations, however. Ever tightening process control limits have led to an increasing need for improved accuracy in the wafer surface characterization methods used in semiconductor chip manufacturing.
By Everest GroupTata Consultancy Services has been recognized as a Leader in the
Everest Group PEAK Matrix for Semiconductor Engineering Services.
In an assessment of 16 leading providers of semiconductor engineering services, TCS was placed highest for
its vision and capability. Highlighted as a key strength was TCS comprehensive portfolio of offerings
covering all service segments and product categories catering to different types of clients. According to the
report, TCS proactively and collaboratively drives innovation in semiconductor engineering engagements
leveraging its strong ecosystem of partners through its inhouse Co-innovation Network. It goes on to say
that the company s robust portfolio of proprietary assets and investments in thought leadership have