Automotive
To support the doubling of bandwidth to 64 GT/s, PCIe 6.0 technology uses PAM4 modulation, which enables it to run 2 bits/cycle compared to the 1 bit/cycle with the previous NRZ modulation. To compensate for the higher BER (Bit Error Rate), XpressRICH for PCIe 6.0 architecture implements FEC (Forward Error Correction) combined with CRC (Cyclic Redundancy Check). XpressRICH for PCIe 6.0 architecture also supports the new L0p low power mode, enabling traffic to be transmitted on a reduced set of lanes, reducing power consumption without impacting traffic flow.
To support configurability for XpressRICH users, PLDA has implemented a large number of features and ECN that can be fully parameterized through the included configuration assistant. Some of these configurable features include:
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Increasing bandwidth to 128 GB/s with a tailored PCIe 6.0 IP Controller
By Romain Tourneau, PLDA
While the PCIe 6.0 specification is expected to be finalized and released later in 2021, PLDA has been hard at work to address the needs of early adopters looking for the most advanced PCIe 6.0 IP solution for their SoCs and ASICs.
Although PCIe 5.0-enabled systems are not yet available in the general market, Automotive, AI and IoT system designers are already pushing for more bandwidth than 5.0 supports. Self-driving cars are the perfect example of this need to continuously sense and react to the surrounding environment in real time, the autonomous driving systems need to access historical data stores containing weather, obstacles, and traffic and road conditions. These enormous data dumps, accounting for every minute, hour, day and year that a driverless car is out on the road, have to be managed and stored. Of course, a large part of a driverless car s environment will be accounti
800G/400G Ethernet Solutions for Networking and Chiplets
Webinar Overview
Ethernet has been used as a mainstream solution for chip-to-chip and die-to-die connectivity. In this webinar, we will review some of the key required features of Ethernet MAC/PCS from 800G down to 10G. We will address various types of Forward Error Correction engines (FEC) to improve the BER of the channel/links. We will analyze how the latest advances in packaging technology have allowed moving the ethernet functions from the main die to chiplets simplifying the system and improving the cost/power/performance of the overall solution.
Key Learnings:
Targeting display applications requiring high bandwidth and excellent power efficiency, this subsystem solution brings a significant improvement in overall throughput available with DSI-2. This level of integration using proven, broadly adopted IP sets a new benchmark for performance, ease of implementation, and time to market. We are excited to announce the combined solution with our Mixel MIPI Central partners, Rambus and Hardent, to fill a gap in the MIPI ecosystem, said Justin Endo, marketing manager at Mixel. Side-by-side instances of our latest generation of C-PHY/D-PHY combo IP support over 60 Gbps aggregate bandwidth without compression, but with it, we can support up to three times that, enabling state-of-the-art performance, and future-proofing our customers designs for years to come.