32-bit Embedded RISC-V Functional Safety Processor 32-bit Embedded RISC-V Functional Safety Processor The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing the RISC-V Instruction Set Architecture (ISA). The Harvard architecture EMSA5 processor implements a single-issue, in-order, 5-stage execution pipeline, supporting the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E). EMSA5 can support machine and user privilege modes, and optionally the standard Multiply (M), Compressed (C), Control and Status Register (Zicsr), and Instruction-Fence (Zifencei) RISC‐V extensions. The processor core communicates with the system via two 32-bit AHB-lite buses (one for data and one for instructions) and its interrupt lines.