Can HLS Partitioning Speed Up Placement and Routing of FPGA

FPGA place-and-route software goes too fast, said no one ever. In fact, FPGA vendors have spent considerable effort in making their design software run faster on multicore processors. A paper recently presented at the ACM’s FPGA 2022 conference titled “RapidStream: Parallel Physical Implementation of FPGA HLS Designs,” describes a very interesting approach to pushing HLS…

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Virtex Ultrascale , Xilinx , Ghent University , Cornell University , Parallel Physical Implementation , Xilinx Virtex , Super Logic Regions , Processing Elements ,