DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Des

The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory ...

Related Keywords

, Digital Blocks , Multi Channel Scatter Gather , Status Register Interface , Axi4 Stream Interface , Xi4 Memory Map , Dma Controller , Ma , Ma Axi4 Stream To From Memory Map Scatter Gather Descriptor List , B Dmac Mc2 Dl Mm2s S2mm , P Core , Ilicon Ip , Emiconductor Ip ,