FPGA Evaluation Platforms for RISC-V Processor Cores This FPGA platform aims to simplify the evaluation of a Codasip low-power (L family) or high-performance (H family) embedded cores. The platform is available to companies with an evaluation agreement. The subsystem is based on AHB and provides a variety of commonly-used peripherals which enable the rapid testing and assessing of a core on an Xilinx-based Digilent Nexys A7 FPGA board. View FPGA Evaluation Platform for Codasip Application Processor RISC-V cores including AHB interconnect and Peripherals full description to... see the entire get in contact with Block Diagram of the FPGA Evaluation Platforms for RISC-V Processor Cores