High performance dual-issue, out-of-order, 7-stage pipeline

RiVAI-R1 is a dual-issue, Out-of-Order execution, 7-stage pipeline, 32-bit RISC-V CPU core IP that supports the RV32IMFAC instruction sets, as well as ...

Related Keywords

, Riscv Cpu Core , Risc V , Riscv , Scalar Core , Uperscalar , Igh Performance Dual Issue , Out Of Order , Stage Pipeline Superscalar Core , Ivai R1 , P Core , Ilicon Ip , Emiconductor Ip ,