MIPI D-PHY TSMC 40LP IP Core : vimarsana.com

The MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. It is a universal PHY that can be configured as a transmitter, receiver or transceiver. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions.

Related Keywords

, Analog Transceiver , Camera Serial Interface , Display Serial Interface , Mipi , Mipid Phy , Mipi Dphy , Cd Phy , Dphy , Mipi Phy , Ipi Physical Layer , Why , D Phy Analog Transceiver , Analog Phy , D Phy Tsmc 40lp , Smc , Ipid Phy 1 , Ipid Phy Tsmc 40lp , Cs Aip Dphy 40lp , P Core , Ilicon Ip , Emiconductor Ip ,