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New Electronics - Riviera-PRO supports system simulation of AMD Versal ACAP designs

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has announced the latest release of the Riviera-PRO, providing support for system simulation of Versal Adaptive Compute Acceleration Platform (ACAP) designs. ....

Pcie Gen , Aldec Github , Network On Chip No , Processing System , Programmable Logic , Louie De Luna ,

Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs

Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs
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Pcie Gen , Aldec Github , Network On Chip No , Aldec Inc , Adaptive Compute Acceleration Platform , Processing System , Programmable Logic , Louie De Luna ,

Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs

Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs
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United States , Aldec Github , Pcie Gen , Amanda Warrilow , Network On Chip No , Aldec Inc , Adaptive Compute Acceleration Platform , Processing System , Programmable Logic , Louie De Luna , Electronic Design ,