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February 23, 2021 // By Nick Flaherty An ARM-based high performance computing (HPC) system-on-chip called Rhea being designed by SiPearl in France will be built in 6nm by TSMC French chip designer SiPearl has teamed with Open-Silicon Research (OSR) in India to develop a 6nm ARM chip for embedded high performance computing (HPC) in 2.5D packaging. The chip, called Rhea, will be based on 64 ARM cores with over 30bn transistors and will be built on TSMC’s 6nm process. This will use the Value Chain Aggregator (VCA) programme through OSR’s US parent company, OpenFive...

Northwest Logic HBM2/2E Controller Core from Rambus tHE High Bandwidth Memory (HBM) DRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by HBM DRAM devices. The core also performs all initialization and refresh functions. The core uses bank management modules to monitor the status of each SDRAM bank (up to 64 banks managed concurrently). Banks are only opened or closed when necessary, minimizing a...