Rambus HBM2/2E Memory PHY IP Core
Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor and power-efficient ...
Source: design-reuse.com
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MIPI M-PHY v3.1 IP in TSMC(12/16nm, 28nm, 40nm, and 55nm)
M31 MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low ...
Source: design-reuse.com
MIPI D-PHY Receiver in TSMC 40nm LP
The MXL-PHY-CSI2-RX+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY. ...
Source: design-reuse.com
HBM Subsystem IP Gen2 IP Core
OpenFive’s HBM IP is the industry’s first comprehensive solution for integrating high-bandwidth memory into ASICs thereby achieving the ultimate high ...
Source: design-reuse.com
MIPI Compliant D-PHY IP Core
The MIPI D-PHY is compliant with the MIPI Alliance Standard for D-PHY.
Source: design-reuse.com