MIPI D-PHY Transmitter - Designed for TSMC 40nmLP for Automotive
The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY.
Source: design-reuse.com
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MIPI D-PHY Receiver IP Core
The MXL-DPHY-CSI2-RX-T-065LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. ...
Source: design-reuse.com
MIPI D-PHY Universal IP in Samsung 28FDSOI
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slave ...
Source: design-reuse.com
MIPI D-PHY Receiver in TSMC 65nm LP
The MIPI D-PHY Receiver is a high-frequency low-power, low-cost, sourcesynchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display interface applications (DSI).
Source: design-reuse.com
MIPI D-PHY Transmitter - Designed for TSMC 40nmLP
The MXL-DPHY-CSI2-TX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for ...
Source: design-reuse.com