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Building a Swiss cheese model approach for processor verification

Processors all have high quality requirements and their reliability is the main concern of processor verification teams. Providing best-in-class quality . ....

Buildinga Swiss Cheese Model Approach For Processor Verification , Codasip Blog , Philippe Luc ,

Measuring the complexity of processor bugs to improve testbench quality

I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and . ....

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality , Codasip Blog , Philippe Luc ,

Closing the Gap in SoC Open Standards with RISC-V

The semiconductor industry has changed hugely in the last 3 or 4 decades. Around 1980 some larger semiconductor companies were strongly vertically integrated, . ....

Closing The Gap In Soc Open Standards With Risc V , Codasip Blog , Roddy Urquhart ,

Improve Your Verification Methodology: Hunt Bugs Flying in Squadrons

Creating a quality RISC-V processor requires a verification methodology that enforces the highest standards. In this article, Philippe Luc, Director of . ....

Philippe Luc , Improve Your Verification Methodology Hunt Bugs Flying In Squadrons , Codasip Blog , Philippe Luc ,