MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 40LP
The MXL-DPHY-CSI-2-RX+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY. ...
Source: design-reuse.com
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MIPI D-PHY 4-Lane CSI2-TX (Transmitter) in TowerJazz 65nm
The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The ...
Source: design-reuse.com
MIPI CSI-2 Receiver
The MIPI CSI-2 Receiver IP is designed to provide MIPI CSI 1.01 compliant high speed serial connectivity for applications processors to corresponding camera modules in mobile platforms.
Source: design-reuse.com
MIPI D-PHY DSI RX (Receiver) in TSMC 65LP
The MIPI D-PHY Receiver is a high-frequency low-power, low-cost, sourcesynchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display interface applications (DSI).
Source: design-reuse.com
MIPI D-PHY CSI-2 RX (Receiver) in Samsung 28FDSOI
The MXL-DPHY-CSI-2-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. ...
Source: design-reuse.com