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LPDDR5/4/4X PHY in TSMC (16nm, 7nm)

The DesignWare LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and systemin-package . ....

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DDR multiPHY in GlobalFoundries (40nm, 28nm)

Synopsys DesignWare® DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L . ....

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DDR3/2 PHY in TSMC (40nm) IP Core

Synopsys DesignWare® DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM . ....

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HBM2 PHY in TSMC (16nm) IP Core

The Synopsys DesignWare® HBM2 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking . ....

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LPDDR4 multiPHY V2 in TSMC (16nm) for Automotive

LPDDR4 multiPHY: Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps - Maximum data rate is process technology dependent - Compatible with JEDEC . ....

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