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CEVA Bluebud - DSP-enabled Bluetooth Audio IP Platform for TWS Earbuds and Wearables All Silicon IP Overview Bluebud™ is a unique self-contained, feature-rich IP platform to streamline the development of True Wireless Stereo (TWS) earbuds and other advanced wireless audio devices including headsets, speakers, smartwatches and smart glasses. It is a unique, pre-integrated hardware and software solution built around the popular and proven RivieraWaves™ Bluetooth IP and CEVA-BX1 audio processor, together with all the required peripherals for wireless audio, in a compact low power design. Blu...

eFPGA IP cores for GF 22FDX The EFLX®4K Logic IP core is an embeddable FPGA IP core containing 2,520 Look-Up-Tables (LUTs: each is 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs) and 21 Kbit RAM, an improved XFLX™ interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time. The EFLX 4K DSP core has 40 DSP MACs (22x22 multiplier with 48 bit accumulator). In the Gen2 architecture, MACs cascade up to 10 stages without using the interconnect network. Each EFLX core is a standalone em...

DVB-S2X WideBand Demodulator IP This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon proven technology. The demodulators are compliant with Annex M of the DVB-S2 specification EN 302 307 and can demodulate signals up to 500 Msymbol/s. Each HSR demodulator may demodulate up to 2 slices. This implements 8 multi-standard demodulators capable of DVB-S, DTV legacy, DVB-S2 and DVB-S2X broadcast-profile signal processing. This IP incorporates a high-speed DVB-S2 forward error corrector (FEC) which...

Aldec enhances Active-HDL to support new features Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has announced that it has enhanced Active-HDL to support new features within VHDL-2019 (IEEE 1076-2019). These new features look to simplify the language, lift certain restrictions that were present in earlier versions and introduce new application programming interfaces (APIs). Support has also been added for release 2020.08 of the open source VHDL verification methodology (OSVVM). Active-HDL is an integra...

MoSys, Inc.: MoSys and Arrow Electronics Collaborate to Optimize System Memory on FPGA Designs SAN JOSE, CA / ACCESSWIRE / January 11, 2021 / MoSys, Inc. (NASDAQ:MOSY) is focused on Accelerating Data Intelligence and provides both semiconductor and IP solutions that enable fast, intelligent data access for Cloud, networking, security and communications systems. Today, MoSys announced an agreement that enables Arrow Electronics, Inc., the world's leading electronics component distributor, to sell MoSys' QPR Memory and Bandwidth Engine memory products and solutions that work with Intel and Xili...