USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use ...
Source: design-reuse.com
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USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use ...
Source: design-reuse.com
MIPI Soundwire PHY IP Core
The physical layer block implements all the line-side functions such as NRZI encoding & decoding, bus clash detection, data line buffer enable/disable. ...
Source: design-reuse.com
Tunable SM3 accelerator IP Core
The SM3 hash algorithm is a cryptographic hash function designed by the Chinese Commercial Cryptography Administration Office (CCCAO) in order to propose ...
Source: design-reuse.com
Tunable DES - Triple DES (ECB, CBC, CTR) accelerator - optional SCA protection
Tunable DES - Triple DES (ECB, CBC, CTR) accelerator - optional SCA protection The Data Encryption Standard (DES) is defined in FIPS PUB 46-3 as a symmetric-key algorithm. The triple DES (TDES) is block cipher that applies the DES algorithm three times to each data block. The TDES is defined in ANS X9.52-1998, NIST SP 800-67 rev-1 and ISO/IEC 18033-3:2010. TDES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting. View see the entire get in contact with Cryptography IP
Source: design-reuse.com