MIPI D-PHY Bidirectional 2 Lanes in GF (40nm, 28nm, 22nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for ...
Source: design-reuse.com
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TSMC 6nm (6FF) 3.3V SMBUS (I2C) IO
Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...
Source: design-reuse.com
USB 3.1/DisplayPort 1.3 Controller IP Solutions IP Core
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offering ...
Source: design-reuse.com
USB-C 3.2 DP/TX PHY in GF (12nm)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or ...
Source: design-reuse.com
ISP, Image Signal Processing, Real-time Pixel Processor for Automotive
Dream Chip’s Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), developed ...
Source: design-reuse.com