Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks
High bandwidth PLL with accurately spaced 16-phase output clocks. Low Power/ Low Area hard macro with industry leading jitter performance for its power/area ...
Source: design-reuse.com
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HDMI 2.1 Audio PLL in Samsung (14nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the ...
Source: design-reuse.com
LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and ...
Source: design-reuse.com
Secure-IC's Securyzr™ Tunable DES - Triple DES (ECB, CBC, CTR) accelerator
The Data Encryption Standard (DES) is defined in FIPS PUB 46-3 as a symmetric-key algorithm. The triple DES (TDES) is a block cipher that applies the ...
Source: design-reuse.com
LPDDR4x/5 Secondary/Slave (memory side!) PHY
This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/LPDDR5 ...
Source: design-reuse.com