Secure-IC's Securyzr™ 1.5Tbps MACsec Engine IP Core
<b>The MACsec Engine implements the latest IEEE 802.1AE specification, providing connectionless data integrity, data origin authenticity and confidentiality ...
Source: design-reuse.com
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12bit 5Msps low power SAR ADC IP core
High performance, 12-bit resolution, 5-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core Node available in 28nm. Leading edge systems on chip ...
Source: design-reuse.com
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory ...
Source: design-reuse.com
Highly scalable performance for classic and generative on-device and edge AI solutions
The Cadence Neo NPUs offer energy-efficient hardware-based AI engines that can be paired with any host processor for offloading artificial intelligence ...
Source: design-reuse.com
IP Camera Front End IP Core
The Bitec Camera Front End IP allows developers to interface CMOS and CCD cameras to an Altera FPGA. Using a memory optimised line buffer, the core sits ...
Source: design-reuse.com