Tessent SoC debug and optimization IP Core
Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs. Leveraging embedded non-intrusive instrumentation ...
Source: design-reuse.com
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112G LR-Max Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performance ...
Source: design-reuse.com
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...
Source: design-reuse.com
16G Ethernet SerDes PHY - GLOBALFOUNDRIES 12nm
The 16 Gbps Ethernet SerDes PHYs is a high-performance serial link subsystem. Optimized for power and area in challenging, high-loss channels typical ...
Source: design-reuse.com
64x8 Bits OTP (One-Time Programmable) IP, UMC 55nm ULP standard CMOS core logic
The AT64X8U55ULP6AA is organized as a 64-word by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 55nm ULP standard ...
Source: design-reuse.com