How really does one design for test? ETC Experts Share their Secrets
The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques. Cadence, Siemens, and Synopsis discussed differing aspects for ongoing test challenges. For example, a scan-based failure diagnosis tool's accuracy, resolution, and performance are extremely critical for enabling faster silicon chip testing and improving overall yields. Scan-based diagnostic methods are used to identify and locate semiconductor defects on devices that fail the manufacturing test...
Source: designnews.com