PCIe 6.0 SerDes PHY IP Core
The Rambus PCI Express® (PCIe®) 6.0 PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility ...
Source: design-reuse.com
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10G/25GBASE-R MAC Core IP Core
The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant with ...
Source: design-reuse.com
50G Ethernet PCS/MAC/FEC IP Core
The fully integrated Physical Coding Sublayer (PCS) and Media Access Controller (MAC) core for 50Gbps Ethernet applications are compliant with IEEE 802.3cd ...
Source: design-reuse.com
800G/400G/200G Ethernet PCS IP Core
The Alphawave CDPCS IP core is a cutting-edge solution to the 800/400/200G Ethernet application. It supports the Physical Coding Sublayer (PCS) for 64B/66B ...
Source: design-reuse.com
10G/25GBASE-R PCS+KR4 FEC IP Core
The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant with ...
Source: design-reuse.com