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Dual-Core HEVC, AV1 & H.264, AVS2, VP9 Combined Decoder The WAVE537 is a dual-core decoder IP, architected for decoding video to 8K60fps(900MHz) in HEVC/H.265, AVC/H.264, VP9, AVS2, AV1 standard formats in real-time with the most optimized size and stable decoding performance. The WAVE537 is cost-effective as it is architected to pick out and reuse sharable blocks from various codec standards and apply them to the common blocks, in which the IP architecture becomes streamlined with minimum logics and memories fitting into small-sized SoCs . The IP provides maximum bandwidth effici...

Read-Modify-Write Core The Read-Modify-Write (RMW) Core from Rambus handles misaligned bursts when an Error Correction Code (ECC) is being used. An ECC code word must be calculated over an entire data word. Misaligned bursts can have partial data words at the front and back end of the burst. To calculate the correct ECC code word, the Read-Modify-Write Core forms the correct starting and ending data words by reading the existing data words and combining them appropriately with the new partial data words. The core performs address translation from byte addressing to the 64-bit or 128-b...

Ethernet MAC 10G/25G Comcores Ethernet MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution. The MAC IP core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum. The core is fully configurable and is prepared for IEEE1588 integration and easy interfacing with Comcores 10G/25G PCS solution. The Ethernet MAC Core, on the Client side, implements a 64-bit AXI-S interface for Express and Preemptable traffic respectively while having a standard XGMII ...

eFPGA IP cores for GF 22FDX The EFLX®4K Logic IP core is an embeddable FPGA IP core containing 2,520 Look-Up-Tables (LUTs: each is 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs) and 21 Kbit RAM, an improved XFLX™ interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time. The EFLX 4K DSP core has 40 DSP MACs (22x22 multiplier with 48 bit accumulator). In the Gen2 architecture, MACs cascade up to 10 stages without using the interconnect network. Each EFLX core is a standalone em...

INSIDE Secure SM4 Engine The EIP-12 SM4 Engine implements the SM4 cipher block algorithm. The accelerator includes I/O registers, encryption and decryption cores. Designed for fast integration, low gate count, and maximum performance, the SM4 Engine provides a reliable and cost-effective SM4 IP solution that is easy to integrate into SoC designs. View see the entire get in contact with SM4 IP