Page 19 - Synopsys Designware News Today : Breaking News, Live Updates & Top Stories | Vimarsana

Highlights: (PRNewsfoto/Synopsys, Inc.) DesignWare Controller, PHY and Verification IP supports the latest features in the PCI Express 6.0 specification, enabling early SoC development Low-latency controller with new MultiStream architecture delivers up to 2X the throughput of a conventional PCI Express controller High-performance PHY in 5-nm process with unique analog and DSP techniques provides 20 percent less power across chip-to-chip, riser card and backplane interfaces Comprehensive set of protocol, methodology and productivity features enable rapid verification of PCI Express 6.0 des...

® EV Development Toolkit. By using Synopsys' programmable ARC EV Processor, Kyocera successfully integrated high-performance artificial intelligence (AI) processing capabilities such as super resolution, with the flexibility to support future AI models. In addition, Kyocera deployed Synopsys' HAPS ® FPGA-based prototyping system to accelerate ARC EV software development, SoC integration, and system validation. "Implementing advanced AI functionality into our MFP SoC required high-performance, low-power processor IP with a high-quality tool chain, allowing us to find and test AI algorithms w...

USB 2.0 femtoPHY in Samsung (14nm, 11nm, 8nm, 7nm, 5nm) The Synopsys DesignWare® USB 2.0 femtoPHY provides designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications such as smartphones, tablets, digital TVs, and media players. Offering reduced silicon cost and longer battery life, the DesignWare USB 2.0 femtoPHY IP delivers 50% smaller die area and minimizes active and suspend power consumption. The DesignWare USB 2.0 femtoPHY implements the latest USB battery charger version 1.2 and USB On-The-Go (OTG) version 2.0 specifications from th...

USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm, 6nm) The Synopsys DesignWare® USB 2.0 femtoPHY provides designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications such as smartphones, tablets, digital TVs, and media players. Offering reduced silicon cost and longer battery life, the DesignWare USB 2.0 femtoPHY IP delivers 50% smaller die area and minimizes active and suspend power consumption. The DesignWare USB 2.0 femtoPHY implements the latest USB battery charger version 1.2 and USB On-The-Go (OTG) version 2.0 specif...

Highlights ® 5.0 or CXL™ 2.0 architectures Pre-verified with DesignWare Controller IP for PCI Express technology and CXL enables fast integration and lowers risk Efficient encryption/decryption and authentication with AES-GCM helps ensure data confidentiality and integrity for high-performance systems Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the DesignWare ® Integrity and Data Encryption (IDE) Security Modules to help designers protect against data tampering and physical attacks in high-performance computing (HPC) SoCs using the PCI Express ® (PCIe ™ (CXL �...